Investigation of the hot carrier degradation in power LDMOS transistors with customized thick oxide

In this paper, we report a combined experimental/simulation analysis of the degradation induced by hot carrier mechanisms, under ON-state stress, in silicon-based LDMOS transistors. In particular, the ON-resistance degradation in linear regime has been experimentally characterized by means of different stress conditions and temperatures. The hot-carrier stress regime has been fully reproduced in the frame of TCAD simulations by using physics-based models able to provide the degradation kinetics. A thorough investigation of the spatial interface trap distribution and its gatebias and temperature dependences has been carried out achieving a quantitative understanding of the degradation effects in the device. Corresponding author. [email protected] Tel: +39 (0547) 338965 Preference: Oral presentation